In recent years, SoC (Silicon on Chip: semiconductor integrated circuit) is utilized in various electronic devices such as a digital still camera (DSC). By the way, following three are generally utilized as a data transfer scheme between respective functional macros (functional blocks, modules) of SoC.
A first data transfer scheme is a transfer by a CPU (Central Processing Unit) on SoC, and a second data transfer scheme is a DMA transfer by DMA controller (Direct Memory Access controller) on a system bus of SoC. In DMA transfer by DMA controller, each functional macro is DMA slave.
A third data transfer scheme performs DMA transfer by implementing a master circuit (DMA master) which performs DMA transfer into functional macro of SoC. In addition, other data transfer schemes are also proposed.
As mentioned above, various schemes such as first to third data transfer schemes are conventionally utilized as data transfer scheme between respective functional macros of SoC, but there are problems in these data transfer schemes as mentioned below.
In first data transfer scheme, the resource for main process to be performed by CPU is consumed since CPU controls data transfer, and therefore the process which CPU originally performs is prevented. In second data transfer scheme, since DMA controller connected to system bus of SoC controls data transfer between a plurality of functional macros, specification of DMA controller is complicated and period for a development is prolonged.
Problem of protraction of development period is come from a matter that, for example, at the time of defining specification of SoC, specification regarding DMA transfer for all functional macros and a priority of processes between all functional macros may have been determined.
Second data transfer scheme also includes a risk that, when using a quality of service (QoS) mechanism, hardware is more complicated, and when QoS mechanism does not suit an actual system operation, it is difficult to satisfy performance of processing speed. Furthermore, when developing another kind of product, there is inconvenience that there are few recyclable parts.
Third data transfer scheme also includes similar problems as second data transfer scheme mentioned above. In other words, transfer specification of DMA including software may be clear at the time of defining specification of SoC.
Third data transfer scheme includes a risk that, when using QoS mechanism, hardware is more complicated, and when QoS mechanism does not suit an actual system operation, it is difficult to satisfy performance of processing speed. Furthermore, when developing another kind of product, there is inconvenience that there are few recyclable parts.
By the way, various systems using a DMA controller are proposed conventionally.
In this regard, in the past, various types of a system employing a DMA controller have been proposed.    Patent Document 1: Japanese Laid-open Patent Publication No. 2005-011287    Patent Document 2: Japanese Laid-open Patent Publication No. H11-041297    Patent Document 3: International Publication Pamphlet No. WO 2008/026273